NDLI: Comparison of 2D median filter hardware implementations for real-time stereo video

Content Provider	IEEE Xplore Digital Library
Author	Scott, J. Pusateri, M. Mushtaq, M.U.
Copyright Year	2008
Description	Author affiliation: Electron. & Comput. Services, Penn State Univ., University Park, PA (Scott, J.; Pusateri, M.; Mushtaq, M.U.)
Abstract	The two-dimensional spatial median filter is a core algorithm for impulse noise removal in digital image processing and computer vision. While the literature presents several analyses of median filters optimized for a standard 3 times 3 pixel neighborhood configuration, a 5 times 5 neighborhood, useful for imagery exhibiting noise not conforming to the classic ldquosalt and pepperrdquo formation, has received little analysis. Research efforts on hardware implementations of median filters have been devoted primarily toward implementations with low latency and high throughput. We are developing a system that includes stereo visible near infrared sensors; both require a 5 times 5 median filter to handle intensifier noise. Since the system is a battery powered unit, optimal power usage is a critical requirement in addition to low latency and high throughput. However, optimal power usage for median filtering has received little attention in the literature. In this paper, we focus on investigating four selected hardware implementations of a 5 times 5 median filter and compare them on the basis of power efficiency. We also analyze the latency, maximum clock rates, and resource utilization for these implementations. The designs include implementations of merge sort and radix sort-based elimination algorithms, common in software implementation of median filters, and a systolic sorting array and a Batcher sorting network, common hardware sorting techniques. All designs were created in the Altera Quartus-II environment for Stratix-II field programmable gate arrays, and were designed to be fully pipelined, accepting input sets and generating median filter output values every pixel clock pulse. Of the four considered designs, the Batcher network is a clear winner in power efficiency. Also, the Batcher network exceeds the functional and performance requirements for resource usage, latency, and clock rate.
Starting Page	1
Ending Page	6
File Size	1286830
Page Count	6
File Format	PDF
ISBN	9781424431250
ISSN	15505219
DOI	10.1109/AIPR.2008.4906464
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Delay Clocks Sorting Stereo vision Image analysis Throughput Digital filters Digital images Computer vision
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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