NDLI: Performance-scalable array architectures for modular multiplication

Content Provider	IEEE Xplore Digital Library
Author	Freking, W.L. Parhi, K.K.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Freking, W.L.)
Abstract	Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. The increasing popularity of Internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.
Starting Page	149
Ending Page	160
File Size	351950
Page Count	12
File Format	PDF
ISBN	0769507166
ISSN	21600511
DOI	10.1109/ASAP.2000.862386
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-07-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Computer architecture Application software Broadcasting Systolic arrays Clocks Scalability Public key cryptography Arithmetic Delay estimation
Content Type	Text
Resource Type	Article

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