NDLI: Implementation of a VLSI polynomial evaluator for real-time applications

Content Provider	IEEE Xplore Digital Library
Author	Corbaz, G. Duprat, J. Hochet, B. Muller, J.-M.
Copyright Year	1991
Description	Author affiliation: Ecole Polytech. Federale de Lausanne, Switzerland (Corbaz, G.)
Abstract	Fast evaluation of polynomials is a major goal of computer science, since any continuous function may be approximated as accurately as desired by a polynomial. For instance, most part of current computers evaluate elementary functions using polynomial or rational approximations. J. Duprat and J.M. Muller (1988) presented a new operator, a polynomier, suitable for VLSI implementation, and specifically designed for polynomials computations. This polynomier is composed of two pipe-lined subparts : a squarer (i.e. an operator able to compute the square of a number), and a binomier (i.e. an element which computes expressions of the form Ax+B). The authors present some possible applications of the polynomier. They recall briefly the main characteristics of the architecture. They describe a VLSI implementation of this architecture and present an extension of this architecture to the two's complement computation.<>
Starting Page	13
Ending Page	24
File Size	408647
Page Count	12
File Format	PDF
ISBN	0818692375
DOI	10.1109/ASAP.1991.238896
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-09-02
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Polynomials Chebyshev approximation Computer architecture Performance evaluation Arithmetic Application software Computer science Approximation algorithms Telecommunication computing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Polynomial evaluation in VLSI using distributed arithmetic

Dual-mode VLSI array for polynomial multiplication using residue arithmetic

VLSI architecture for the efficient computation of line spectral frequencies

VLSI implementation of a real-time operating system

Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

A VLSI inner product macrocell

VLSI implementation of pipelined linear system solver

New $2^{n}DCT$ algorithms suitable for VLSI implementation

High performance VLSI architecture for data clustering targeted at computer vision

Implementation of a VLSI polynomial evaluator for real-time applications

Similar Documents

Polynomial evaluation in VLSI using distributed arithmetic

Dual-mode VLSI array for polynomial multiplication using residue arithmetic

VLSI architecture for the efficient computation of line spectral frequencies

VLSI implementation of a real-time operating system

Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

A VLSI inner product macrocell

VLSI implementation of pipelined linear system solver

New $2^{n}DCT$ algorithms suitable for VLSI implementation

High performance VLSI architecture for data clustering targeted at computer vision

Implementation of a VLSI polynomial evaluator for real-time applications