NDLI: MOVIE: a building block for the design of real time simulator of moving pictures compression algorithms

Content Provider	IEEE Xplore Digital Library
Author	Barzic, R. Bouville, C. Charot, F. Le Fol, G. Lemonnier, P. Wagner, C.
Copyright Year	1995
Description	Author affiliation: CCETT, Cesson Sevigne, France (Barzic, R.; Bouville, C.; Charot, F.; Le Fol, G.)
Abstract	This paper shows how a real-time simulator of moving pictures compression algorithms can be rapidly assembled using a basic building block, here called MOVIE (MOdule for Video Experimentation). The internal architecture of the MOVIE VLSI chip can be compared to a small systolic machine made of a 32-bit I/O processor, a reduced linear array of 16-bit computation processors and data video input/output mechanisms. Externally, the chip is provided with four 16-bit bidirectional data ports and three 16-bit bidirectional data video port. Several MOVIE chips can be easily clustered to allow the size of the linear array of computation processors to be increased. The MOVIE chip is fully programmable in a high level language in order to make program developments easier.
Starting Page	193
Ending Page	203
File Size	686873
Page Count	11
File Format	PDF
ISBN	0818671092
ISSN	10636862
DOI	10.1109/ASAP.1995.522923
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-07-24
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion pictures Video compression Signal processing algorithms Computer architecture Very large scale integration Transform coding Digital signal processing chips Compression algorithms Concurrent computing Hardware
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 4-way pipelined processing architecture for three-step search block-matching motion estimation

A 4-way pipelined processing architecture for three step search block-matching motion estimation

An Area Efficient High Performance DCT Distributed Architecture for Video Compression

Parallelizing Motion JPEG 2000 with CUDA

A single chip processor architecture for video rate two-dimensional digital filtering

A DSP-coprocessor architecture for image/video applications [coding/decoding]

VLSI architectures for block matching algorithms using systolic arrays

Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator

Three goals in designing VLSI architectures for video compression

MOVIE: a building block for the design of real time simulator of moving pictures compression algorithms

Similar Documents

A 4-way pipelined processing architecture for three-step search block-matching motion estimation

A 4-way pipelined processing architecture for three step search block-matching motion estimation

An Area Efficient High Performance DCT Distributed Architecture for Video Compression

Parallelizing Motion JPEG 2000 with CUDA

A single chip processor architecture for video rate two-dimensional digital filtering

A DSP-coprocessor architecture for image/video applications [coding/decoding]

VLSI architectures for block matching algorithms using systolic arrays

Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator

Three goals in designing VLSI architectures for video compression

MOVIE: a building block for the design of real time simulator of moving pictures compression algorithms