NDLI: Polychrony for formal refinement-checking in a system-level design methodology

Content Provider	IEEE Xplore Digital Library
Author	Talpin, J.-P. Le Guernic, P. Shukla, Sandeep Kumar Gupta, Rajesh Doucet, F.
Copyright Year	2003
Description	Author affiliation: IRISA, Rennes, France (Talpin, J.-P.; Le Guernic, P.)
Abstract	The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating factors for widespread adoption of these new paradigms is a lack of formal tool support of refinement based design. A system level representation may be refined manually (in absence of adequate behavioral synthesis algorithms and tools) to obtain an implementation, but proving that the lower level representation preserves the correctness proved at higher level models is still an unsolved problem. We address the issue of formal refinement proofs between design abstraction levels using the concepts of polychronous design. Refinement of synchronous high-level designs into globally asynchronous and locally synchronous architectures is formally supported in this methodology. The polychronous (i.e. multiclocked) model of the SIGNAL design language offers formal support for the capture of behavioral abstractions for both very high-level system descriptions (e.g. SYSTEMC/SPEcC,) and behavioral-level IP components (e.g. VHDL). Its platform, polychrony, provides models and methods for a rapid, refinement-based, integration and a formal conformance-checking of GALS hardware/software architectures. We demonstrate the effectiveness of our approach by the experimental, comparative, case study of an even-parity checker design in SPEcC. It highlights the benefits of the formal models, methods and tools provided in polychrony, in representing functional, architectural, communication and implementation abstractions of the design, and the successive refinements.
Sponsorship	IFIP WG10.5 and SIG-ES Colegio de Engenharia Informatica da Ordem dos Engenheiros Portuguesa FME - Formal Methods Europe ACM Special Interest Group on Software Eng. ACM Special Interest Group on Design Autom. Eur. Union Asynchronous Circuit Design Working Group
Starting Page	9
Ending Page	19
File Size	883913
Page Count	11
File Format	PDF
ISBN	0769518877
DOI	10.1109/CSD.2003.1207695
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-20
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-level design Concurrent computing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Polychrony for Formal Refinement-Checking in a System-Level Design Methodology

Formal refinement checking in a system-level design methodology (2004).

Polychrony for Formal Refinement-Checking in a System-Level Design Methodology (2003)

Formal refinement checking in a system-level design methodology,” Fundamenta Informaticae (2004)

Formal refinement-checking in a system-level design methodology

Ios press formal refinement-checking in a system-level design methodology.

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Polychrony for formal refinement-checking in a system-level design methodology

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