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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Barnwell, T. Hodges, C. Randolph, M. |
| Copyright Year | 1982 |
| Description | Author affiliation: Georgia Institute of Technology, Atlanta, GA, USA (Barnwell, T.) |
| Abstract | This paper summarizes the results of a theoretical and experimental study of a general technique for the implementation of recursive and nonrecursive signal flow graphs and other arithmetic algorithms on synchronous digital machines composed of many identical programmable processors. This technique can be characterized by two fundamental properties. First, it uses the Skewed Single Instruction Multiple Data (SSIMD) mode in which exactly the same program is executed on all the processors [1], and that program is exactly a single processor realization of the entire algorithm being implemented. Second, all the data precedence relations among the processors are automatically maintained by the inherent synchrony of the system. This often results in processor-optimum solutions in which the use of M processors leads exactly to an M-fold increase in the system throughput. In the final analyses, the techniques discussed here result in a procedure in which the algorithm is specified in some simple notation, such as a set of difference equations, and from this a completely parallel multiprocessor implementation for the algorithm is generated. The resulting implementation is always either processor-optimum or time-optimum in which the absolute throughput limit for the technique has been reached. In addition, for a large class of recursive signal flow graphs, the implementations are absolute-optimum in the sense that there is no other implementation for a particular signal flow graph and a particular constituent processor which ever leads to greater systems throughput. The techniques discussed here have been tested on a synchronous multiprocessor system [1][2][3]. |
| Starting Page | 679 |
| Ending Page | 682 |
| File Size | 88130 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ICASSP.1982.1171537 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1982-05-03 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flow graphs Delay effects Throughput Delay systems Tin Time measurement |
| Content Type | Text |
| Resource Type | Article |
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