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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Castellino, P. Scagliola, C. |
| Copyright Year | 1977 |
| Description | Author affiliation: CSELT-Centro Studi e Laboratori Telecomunicazioni, Torino, Italy (Castellino, P.) |
| Abstract | In instantaneously companded delta modulators, the step-size is multiplied, at each sampling time, by an expansion-- compression factor depending on the sequence of the M most recent output bits. Some authors determined the values of the multipliers by optimizing the S/N ratio on a typical signal. This procedure can be effectively used only when a small number of bits is observed, but it becomes very heavy when that number grows up to 4 or 5. Starting from simple observations of ideal waveform tracking, a learning algorithm is given in this paper, which permits to calculate easily the values of the multipliers for any bit sequence length, which are tailored to the statistical properties of the signal used in the learning stage. This algorithm automatically permits to take into account even the particular predictor used in the delta feedback loop. The multiplier design is exploited for speech signals in various circuit conditions i.e. clock rate, predictor complexity and length of the bit sequence. The modulator performances are evaluated even as a function of the input signal level. |
| Starting Page | 196 |
| Ending Page | 199 |
| File Size | 109600 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ICASSP.1977.1170361 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1977-05-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delta modulation Logic Sampling methods Feedback Speech Circuits Telecommunications Signal design Clocks Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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