NDLI: Efficient Embedded Neural-Network-Based License Plate Recognition System

Content Provider	IEEE Xplore Digital Library
Author	Caner, H. Gecim, H.S. Alkar, A.Z.
Copyright Year	1967
Abstract	In this paper, a video processing methodology for a field-programmable gate array (FPGA)-based license plate recognition (LPR) system is researched. The raster scan video is used as an input with low memory utilization. During the design, Gabor filter, threshold, and connected component labeling (CCL) algorithms are used to obtain license plate region. This region is segmented into disjoint characters for the character recognition phase, where the self-organizing map (SOM) neural network is used to identify the characters. The system is portable and relatively faster than computer-based recognition systems. The robustness of the system has been tested with a large database acquired from parking lots and a highway. The memory requirements are uniquely designed to be extremely low, which enables usage of smaller FPGAs. The resulting hardware is suitable for applications where cost, compactness, and efficiency are system design constraints.
Sponsorship	IEEE Vehicular Technology Society
Starting Page	2675
Ending Page	2683
Page Count	9
File Size	819053
File Format	PDF
ISSN	00189545
Volume Number	57
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Licenses Field programmable gate arrays Algorithm design and analysis Gabor filters Labeling Character recognition Neural networks Portable computers Robustness System testing self-organizing maps (SOMs) field-programmable gate arrays (FPGAs) neural network applications neural networks Field Programmable Gate Arrays Self-organizing maps Neural networks applications
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Automotive Engineering Computer Networks and Communications Electrical and Electronic Engineering Aerospace Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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