NDLI: Design of Synthetic Quasi-TEM Transmission Line for CMOS Compact Integrated Circuit

Content Provider	IEEE Xplore Digital Library
Author	Meng-Ju Chiang Hsien-Shun Wu Tzuang, C.-K.C.
Copyright Year	1963
Abstract	This paper presents the design guidelines of the synthetic quasi-TEM transmission line (TL) based on standard 0.18 mum one-poly six-metal complementary metal-oxide-semiconductor (CMOS) technology. The synthetic quasi-TEM TL, also called the complementary-conducting-strip transmission line (CCS TL), is composed of five structural parameters to synthesize its guiding characteristics. Twenty-four designs of CCS TL are reported, with the following unique attributes. First, a characteristic impedance range of 8.62-104.0 Omega is yielded. Second, the maximum value of the slow-wave factor is 4.79, representing an increase of 139.5% over the theoretical limit of the quasi-TEM TL. Third, the ratio of the area of the CCS TL to its corresponding quality factor ( factor) can help to estimate the cost of the loss for the circuit miniaturizations. Additionally, the important CMOS manufacturing of metal density is for the first time involved in the reported TL designs. By following the proposed design methodologies, a practical design example of a -band CMOS rat-race hybrid is reported and experimentally examined in detail to reveal the feasibility of the proposed design guidelines to synthesize the CMOS CCS TL. The chip size without contact pads is 420.0 mum 540.0 mum. The measured loss and isolation of the hybrid at 36.3 GHz are 3.84 and 58.0 dB, respectively.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	2512
Ending Page	2520
Page Count	9
File Size	2218046
File Format	PDF
ISSN	00189480
Volume Number	55
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Distributed parameter circuits CMOS integrated circuits Integrated circuit synthesis Carbon capture and storage Transmission line theory Guidelines CMOS technology Design methodology Integrated circuit technology Structural engineering transmission line (TL) Complementary metal–oxide–semiconductor (CMOS) hybrid quasi-TEM thin-film microstrip (TFMS)
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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