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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nayak, A.R. Barry, R. McLaughlin, W. |
| Copyright Year | 1965 |
| Abstract | We consider the problem of training symbol placement for timing acquisition in digital magnetic recording systems that can be modeled as band-limited, baud-rate sampled systems with intersymbol interference and frequency offset. The conventional approach is to place known symbols at the start of the sector and use these at the detector to run a trained phase-locked loop (PLL). We introduce an additional degree of freedom by allowing arbitrary locations for the training symbols. We first consider a simplified system model where only the training symbols are written, or equivalently, the unknown data is assumed to be zero. We derive the modified Cramer-Rao bound (CRB) on the timing estimation error variance as a function of the training symbol locations and then derive the optimal training symbol placement strategy to minimize the CRB. The optimal strategy, called the split-preamble strategy, is to split the known symbols into two halves and place these at the beginning and at the end of the sector. Simulations with a proposed PLL-based method show that the split-preamble arrangement leads to a reduced frequency estimation error variance and also greatly reduces the occurrence of lost or added symbols, i.e., cycle slips. Finally, we present a simplified analysis of the problem when both known and unknown data are present, and show that the same arrangement also minimizes the CRB in this case |
| Sponsorship | IEEE Magnetics Society |
| Starting Page | 1730 |
| Ending Page | 1742 |
| Page Count | 13 |
| File Size | 349376 |
| File Format | |
| ISSN | 00189464 |
| Volume Number | 42 |
| Issue Number | 6 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-06-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency Timing Phase locked loops Detectors Channel estimation USA Councils Phase detection Fading Digital magnetic recording Intersymbol interference training symbol placement CramÉr-Rao bound frequency offset phase-locked loop timing acquisition |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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