NDLI: Multiple serial and parallel concatenated single parity-check codes

Content Provider	IEEE Xplore Digital Library
Author	Tee, J.S.K. Taylor, D.P. Martin, P.A.
Copyright Year	1972
Abstract	Single parity-check (SPC) codes are applied in both parallel and serial concatenated structures to produce high-performance coding schemes. The number of concatenations or stages, M, is increased to improve system performance at moderate-to-low bit-error rates without changing the overall code parameters (namely, code rate and code block length). Analytical bounds are presented to estimate the performance at high signal-to-noise ratios. The SPC concatenated codes are considered with binary phase-shift keying and with 16-quadrature amplitude modulation bit-interleaved coded modulation on the additive white Gaussian noise channel and the independent Rayleigh fading channel. Simulations show that the four-stage serial or parallel concatenated SPC codes can, respectively, outperform or perform as well as 16-state turbo codes. Furthermore, decoding complexity is approximately 9-10 times less complex than that of 16-state turbo codes. The convergence behavior of both serial and parallel concatenated SPC codes is also discussed.
Starting Page	1666
Ending Page	1675
Page Count	10
File Size	833369
File Format	PDF
ISSN	00906778
Volume Number	51
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concatenated codes Parity check codes Amplitude modulation Turbo codes System performance Bit error rate Signal analysis Performance analysis Signal to noise ratio Phase shift keying
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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