NDLI: Randomized routing of virtual connections in essentially nonblocking log N-depth networks

Content Provider	IEEE Xplore Digital Library
Author	Szymanski, T. Chien Fang
Copyright Year	1972
Abstract	An optimal N/spl times/N circuit switching network with /spl theta/(N/spl times/N) bandwidth has a lower bound of /spl theta/(N/spl middot/log N) hardware, which includes all crosspoints, bits of memory and logic gates, and a lower bound of /spl theta/(logN) set-up time. To date no known self-routing circuit switching networks with explicit constructions achieve these lower bounds. The authors consider a randomized routing algorithm on a class of circuit switching networks called "extended dilated banyans". It is proven that the blocking probability of an individual connection request is O[log/sub b/ N/spl middot/(k/d)/sup d/], where d is the dilation factor and k is a constant. With a dilation of /spl theta/(log log N) and a loading <1 the blocking probability is shown to approach zero, yielding an "essentially nonblocking" network. The hardware complexity of these networks depends upon the internal node implementation. A space division node yields a network with /spl theta/(N/spl middot/log N/spl middot/log log N) hardware and /spl theta/(log N/spl middot/log log N) set-up time. A time division node, in which the bits from each connection are dynamically concentrated in time using a "time-bit-concentrator" circuit, yields a network with an asymptotically optimal O(N/spl middot/log N) hardware and a slightly suboptimal /spl theta/(log N/spl middot/log log N) set-up time. Both implementations improve upon the best known explicit constructions of self-routing circuit switching networks with /spl theta/(N) bandwidth, and the TDM construction meets Shannon's lower bound on the cost of such networks. It is shown that extended dilated banyans can carry significantly more traffic than the Batcher-banyan switch and its variants.<>
Starting Page	2521
Ending Page	2531
Page Count	11
File Size	1125730
File Format	PDF
ISSN	00906778
Volume Number	43
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Switching circuits Hardware Bandwidth Switches Logic gates Logic circuits Time division multiplexing Costs Telecommunication traffic
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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