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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ogmundson, P.G. Driessen, P.F. |
| Copyright Year | 1972 |
| Abstract | A digital phase-locked loop (DPLL) bit synchronizer that tracks the zero crossings of a bandlimited binary signal is discussed. The synchronizer reduces pattern jitter or self noise with a compensation signal in the synchronizer feedback loop without using a prefilter. Analytical results are derived for the timing jitter variance (additive noise and self noise) of the synchronizer. Computer simulations and laboratory measurements are shown to verify the effectiveness of the pattern jitter compensation techinque for a synchronizer operating with both spectral raised cosine signaling pulses as well as for signaling pulses generated by a realizable filter network. Implementation of the pattern jitter compensation method in an adaptive synchronizer structure for applications where a priori knowledge of the signaling pulse shape is not available is also discussed.< |
| Starting Page | 603 |
| Ending Page | 612 |
| Page Count | 10 |
| File Size | 843801 |
| File Format | |
| ISSN | 00906778 |
| Volume Number | 39 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-04-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pulse measurements Additive noise Phase locked loops Tracking loops Noise reduction Feedback loop Analysis of variance Timing jitter Computer simulation Laboratories |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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