NDLI: Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel

Content Provider	IEEE Xplore Digital Library
Author	Provence, J.D. Gupta, S.C.
Copyright Year	1972
Abstract	The theory and design of systolic arrays for Viterbi processing in communication systems with a time-dispersive time-varying channel is discussed. The architecture, algorithms, and processor elements, for a two-dimensional systolic array are described. The array supports the branch metric computations required for an adaptive Viterbi processor. The array is designed so that computations propagate along the rows of the array, while data symbols propagate along the columns. All interprocessor data flow and connections within the array are nearest-neighbor. The array illustrates how the Viterbi-processor algorithms can be structured to achieve a high degree of computational concurrency. Variations in the array design are described and evaluated in terms of computational resource requirements and utilization and computational throughput. A high-bandwidth memory interface is proposed, and system design considerations are discussed.<>
Starting Page	1148
Ending Page	1156
Page Count	9
File Size	965791
File Format	PDF
ISSN	00906778
Volume Number	36
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Systolic arrays Viterbi algorithm Maximum likelihood estimation Throughput Data communication Communication systems Adaptive arrays Concurrent computing Bandwidth Baseband
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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