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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ono, R. Beall, J. Harris, R. |
| Copyright Year | 1965 |
| Abstract | Using niobium edge junctions and electron beam lithography (EBL) we have made direct coupled logic (DCL) OR gates with 1 μm minimum line widths. The gate cell, containing an isolator and a buffer section, fits into an area of approximately 25 by 30 μm2. Our computer simulations show that these gates can have switching times of less than 10 ps. We have simulated the DCL circuit with several values of the most space-consuming element, an inductor. This paper describes the results of these simulations and presents a detailed description of the 7-level fabrication process. The mix of optical and electron-beam lithography used relies heavily on an inexpensive, yet powerful, circuit layout program. |
| Sponsorship | IEEE Magnetics Society |
| Starting Page | 846 |
| Ending Page | 849 |
| Page Count | 4 |
| File Size | 545991 |
| File Format | |
| ISSN | 00189464 |
| Volume Number | 21 |
| Issue Number | 2 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1985-03-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fabrication Lithography Computational modeling Circuit simulation Niobium Electron beams Optical coupling Logic gates Isolators Computer simulation |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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