NDLI: Point defect yield model for wafer scale integration

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Point defect yield model for wafer scale integration

Content Provider	IEEE Xplore Digital Library
Author	Ketchen, M.B.
Copyright Year	1988
Abstract	Yield projections are a primary consideration in wafer scale integration. The author develops a point defect yield model for a two-way redundancy scheme appropriate for random logic. The model assumes that the fault-causing defects are randomly distributed locally but that the defect density can vary across a wafer as well as from one wafer to another. Examples are given to illustrate the strong dependence of the results on clustering of defects and on the redundancy partitioning. The importance of the distinction between on-wafer and wafer-to-wafer variations in defect density is demonstrated. Complications associated with the occurrence of small numbers of highly correlated defects are discussed.
Starting Page	24
Ending Page	34
Page Count	11
File Size	25170476
File Format	PDF
ISSN	87553996
Volume Number	1
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-07-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Redundancy Distribution functions Semiconductor device modeling Equations Wafer scale integration Fabrication
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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