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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Murakami, H. |
| Copyright Year | 1965 |
| Abstract | A method is presented for using imperfect bubble chips having a major/minor loop scheme. The imperfect chips are allocated in a memory module in such a manner that defective minor loop groups are arranged in a predetermined regular relationship with respect to the positions of the defective groups within the chips. A statistical analysis is presented to determine the value of chip yield under the condition that existense of one or more defective groups within a chip are permissible. A memory system cost reduction of up to 50 percent is demonstrated for the fault-tolerant scheme chosen as an example, since the addition of the electronic circuit which enables the use of the imperfect chips is very simple. |
| Sponsorship | IEEE Magnetics Society |
| Starting Page | 1631 |
| Ending Page | 1635 |
| Page Count | 5 |
| File Size | 490399 |
| File Format | |
| ISSN | 00189464 |
| Volume Number | 13 |
| Issue Number | 5 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1977-09-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fault tolerance Assembly Fault tolerant systems Statistical analysis Costs Electronic circuits Memory management Production systems |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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