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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lee, C.-Y. Hsieh, P.-H. Yang, C.-H. |
| Copyright Year | 2004 |
| Abstract | This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9 |
| Sponsorship | IEEE Circuits and Systems Society |
| Starting Page | 70 |
| Ending Page | 79 |
| Page Count | 10 |
| File Size | 2833456 |
| File Format | |
| ISSN | 15498328 |
| Volume Number | 63 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2016-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Adiabatic CMOS integrated circuits Computer architecture Recycling Clocks Rails Finite impulse response filters power minimization Adiabatic logic energy recycling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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