NDLI: A Wide-Angle Scanning and Low Sidelobe Level Microstrip Phased Array Based on Genetic Algorithm Optimization

Content Provider	IEEE Xplore Digital Library
Author	Ya-Qing Wen Bing-Zhong Wang Xiao Ding
Copyright Year	1963
Abstract	In order to obtain a wide-angle scanning and low sidelobe level (SLL) microstrip phased array with a finite metal ground, a novel microstrip phased array based on microstrip magnetic dipole is presented in this communication. Microstrip magnetic dipoles are employed as the driven elements in the phased array. Meanwhile, coupling patches are embedded between the adjacent driven elements, and coupling energy is transferred between driven elements by the coupling patches. Strong coupling has been constructed between elements as the driven element spacing is only about 0.35 λ . With the influence of adjacent elements, the 3-dB beamwidth (BW) of each active element can reach over ±80° in the elevation plane. From simulation and measurement, the main lobe scanning ranges of an 8-element and a 16-element phased arrays can both extend over ±80° in the elevation plane with a gain fluctuation less than 3 dB. Furthermore, in order to keep the SLL low in the scanning, especially at the low elevation angles, genetic algorithm (GA) has been used, and the SLL has been decreased to the value of -9 dB in the full scanning range of ±77° for the eight-element array.
Sponsorship	IEEE Antennas and Propagation Society
Starting Page	805
Ending Page	810
Page Count	6
File Size	968412
File Format	PDF
ISSN	0018926X
Volume Number	64
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arrays Couplings Microstrip Finite element analysis Microstrip antenna arrays Metals Antenna radiation patterns genetic algorithm Microstrip magnetic dipole phased array wide-angle scanning low sidelobe level Genetic algorithm (GA) low sidelobe level (SLL) microstrip magnetic dipole
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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