NDLI: An experimental 224 mb/s digital multiplexer-demultiplexer using pulse stuffing synchronization

Content Provider	IEEE Xplore Digital Library
Author	Witt, F. J.
Copyright Year	1922
Description	Solid-state device and circuit technology has advanced to the point where processing of digital signals with bit rates as high as 224 Mb/s may be accomplished. As a specific demonstration of this fact, an experimental mutliplexer-demultiplexer has been developed which combines the following signals into a 224 Mb/s binary pulse train for transmission over a digital transmission network and which furnishes the necessary processing to reconstitute the original signal components: i) A PCM-coded commercial color video signal (111.2 Mb/s) ii) A PCM-coded FDM mastergroup signal (55.6 Mb/s) iii) Two T1 carrier (24 voice channel TDM) signals (1.544 Mb/s each) iv) Word generator signals to occupy the remaining time slots. The line bit rate is derived from and is therefore synchronous with the coded video signal; however, the coded mastergroup and T1 carrier signals are derived from independent clocks. Synchronization of the latter two signal types has been achieved through the use of pulse stuffing synchronization with added-bit synchronization signaling. The ability of a 224 Mb/s buffer memory coupled with a phase-locked loop to attenuate adequately the timing jitter which accumulates in a long digital transmission network has also been demonstrated. All of the experimental results have indicated that the realization of a commercial high-speed digital multiplexer-demultiplexer is feasible.
Starting Page	1843
Ending Page	1885
Page Count	43
File Size	5479343
File Format	PDF
ISSN	00058580
Volume Number	44
Issue Number	9
Language	English
Publisher	American Telephone and Telegraph Company (AT&T)
Publisher Date	1965-01-01
Access Restriction	Subscribed
Rights Holder	Bell Labs
Content Type	Text
Resource Type	Article
Subject	Engineering

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