NDLI: Junctionless Poly-Si Nanowire FET With Gated Raised S/D

Content Provider	IEEE Xplore Digital Library
Author	Chen, L. Yeh, M. Lin, K. Wu, M. Wu, Y.
Copyright Year	2013
Abstract	The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefore, a JL poly-Si NW-FET with the gated raised S/D exhibits reduced drain-induced barrier lowering and less channel length modulation effect. Additionally, when the gate bias exceeds the flat-band voltage, a JL poly-Si NW-FET with gated raised S/D exhibits a low parasitic S/D resistance owing to the formation of an accumulation layer in its S/D, which is useful for multi-gate-oxide applications. However, the gated raised S/D shows a high gate-induced drain leakage current in the off state. Therefore, the gate electrode of the gated raised S/D must be designed carefully to prevent high off current.
Starting Page	50
Ending Page	54
Page Count	5
File Size	1242875
File Format	PDF
ISSN	21686734
Volume Number	4
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Field effect transistors Immune system Silicon Nanoscale devices CMOS integrated circuits system-on-chip (SOC) junctionless field-effect transistor(JL FET) nanowire (NW)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering Biotechnology

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