NDLI: Determination of Wafer Start Mix in Semiconductor Manufacturing During New Technology Ramp-Up: Model, Solution Method, and an Empirical Study

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Determination of Wafer Start Mix in Semiconductor Manufacturing During New Technology Ramp-Up: Model, Solution Method, and an Empirical Study

Content Provider	IEEE Xplore Digital Library
Author	Kuo-Hao Chang Hsieh, L.Y.
Copyright Year	2013
Abstract	In semiconductor manufacturing, production ramp-up is a necessary phase before a new technology is introduced because it affects not only the time-to-market, but also the time-to-volume (the time to reach mass production). In production ramp-up, engineering lots are implemented in order to collect data for product and equipment qualification, and they are expected to achieve short cycle times (CTs) and high throughputs. On one hand, the increment of the amount of engineering lots will disrupt the smoothness of the manufacturing flow and cause work-in-process (WIP) bubbles. On the other hand, to ensure the feasibility of the production plan, some throughput and CT targets must be achieved. There is a need to determine an appropriate wafer start mix to strike a balance between the conflicting objectives. However, the complexity and stochasticity existing in the semiconductor manufacturing process makes it a very difficult task. This paper modeled the wafer start mix determination problem and proposed an efficient methodology, called progressive simulation optimization (PSO), based on the simulation metamodeling techniques to handle this problem. The goal was to find the optimal wafer start mix that enables maximum throughput of engineering lots, while satisfying the requirement of CT of normal lots (NL). A numerical study was conducted to evaluate the performance of the proposed PSO, and an empirical study based on real data was conducted to validate the viability of the proposed methodology in practice.
Starting Page	294
Ending Page	302
Page Count	9
File Size	1142517
File Format	PDF
ISSN	21682216
Volume Number	46
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Throughput Manufacturing processes Metamodeling wafer start mix Semiconductor manufacturing simulation metamodeling
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Information Systems Human-Computer Interaction Electrical and Electronic Engineering Computer Science Applications Software

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