NDLI: W-Band CMOS 4-Bit Phase Shifter for High Power and Phase Compression Points

Content Provider	IEEE Xplore Digital Library
Author	Hyo-Sung Lee Byung-Wook Min
Copyright Year	2004
Abstract	A CMOS 4-bit phase shifter is designed for W-band applications using a 65-nm CMOS process. Switched-delay-type 90°, 45°, and 22.5° 1-bit phase shifters are designed to have high power-handling capability using a signal line bias voltage. The power and phase compression of 90°, 45°, and 22.5° phase shifters are analyzed, and the phase shifters are optimally cascaded for high power and phase compression points. The measured insertion loss of the 4-bit phase shifter is -25 ± 2.1 dB, and the root mean square (RMS) gain error of the 16 different phase states is 1.1 dB at 77 GHz. An input and output return loss is less than -8 dB at 70-85 GHz. The phase shifter has the RMS phase error of 7.20 at 77 GHz and is less than 11.25° at 75-85 GHz. The measured minimum 1-dB power compression point of 16 different phase states is 15.0 dBm. The high input power also compresses the phase adjustment range and increases the phase error, which is limited to 11.25° up to the input power of 21 dBm. The phase shifter consumes no dc current and occupies a small chip area of 0.122 mm², excluding pads.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1
Ending Page	5
Page Count	5
File Size	743599
File Format	PDF
ISSN	15497747
Volume Number	62
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase shifters CMOS integrated circuits Phase measurement Insertion loss Switches Power measurement Switching circuits phase compression point Phase shifter CMOS switch phase error power compression point phase shifter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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