NDLI: GPUSCAN: GPU-Based Parallel Structural Clustering Algorithm for Networks

Content Provider	IEEE Xplore Digital Library
Author	Stovall, T.R. Kockara, S. Avci, R.
Copyright Year	1990
Abstract	This paper presents a massively parallel implementation of a prominent network clustering algorithm, the structural clustering algorithm for networks (SCAN), on a graphical processing unit (GPU). SCAN is a fast and efficient clustering technique for finding hidden communities and isolating hubs/outliers within a network. However, for very large networks, it still takes considerable amount of time. With the introduction of massively parallel Compute Unified Device Architecture (CUDA) by Nvidia, applications properly employing GPUs are demonstrating high speed up. In current study, GPUSCAN, a CUDA based parallel implementation of SCAN, is presented. SCAN's computation steps have been carefully redesigned to run very efficiently on the GPU by transforming SCAN into a series of highly regular and independent concurrent operations. All intermediate data structures are created in the GPU to efficiently benefit from GPU's memory hierarchy. How these structures reformed and represented in the GPU memory hierarchy are illustrated. Now, through GPUSCAN, a large network or a batch of disjoint networks can be offloaded to the GPU for very fast and equivalent structural clustering. The performance of the GPU accelerated structural clustering has been shown to be much faster than the sequential CPU implementation. Both GPUSCAN and SCAN are tested on different size artificial and real-world networks. Results indicate that network becomes larger GPUSCAN significantly over performs SCAN. In tested datasets, speed-up of over 500-fold is achieved. For instance, calculating structural similarity and clustering of 5.5 million edges of the California road network in GPUSCAN is 513-fold faster than the serial version of SCAN.
Sponsorship	IEEE Computer Society
Starting Page	3381
Ending Page	3393
Page Count	13
File Size	1010075
File Format	PDF
ISSN	10459219
Volume Number	26
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics processing units Clustering algorithms Instruction sets Algorithm design and analysis social networks structural clustering for networks GPGPU high-performance computing very large networks Structural clustering for networks
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computational Theory and Mathematics Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient GPU Implementation of Inclusion-Based Pointer Analysis

A Scalable Work-Efficient and Depth-Optimal Parallel Scan for the GPGPU Environment

Computing Nash Equilibria in Bimatrix Games: GPU-Based Parallel Support Enumeration

IMGPU: GPU-Accelerated Influence Maximization in Large-Scale Social Networks

Design and Performance Evaluation of Image Processing Algorithms on GPUs

A Parallel Algorithm for Game Tree Search Using GPGPU

A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs

GPU Computing for Parallel Local Search Metaheuristic Algorithms

HARP: an open architecture for parallel matrix and signal processing

GPUSCAN: GPU-Based Parallel Structural Clustering Algorithm for Networks

Similar Documents

An Efficient GPU Implementation of Inclusion-Based Pointer Analysis

A Scalable Work-Efficient and Depth-Optimal Parallel Scan for the GPGPU Environment

Computing Nash Equilibria in Bimatrix Games: GPU-Based Parallel Support Enumeration

IMGPU: GPU-Accelerated Influence Maximization in Large-Scale Social Networks

Design and Performance Evaluation of Image Processing Algorithms on GPUs

A Parallel Algorithm for Game Tree Search Using GPGPU

A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs

GPU Computing for Parallel Local Search Metaheuristic Algorithms

HARP: an open architecture for parallel matrix and signal processing

GPUSCAN: GPU-Based Parallel Structural Clustering Algorithm for Networks