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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Scogland, T.R.W. Wu-Chun Feng Rountree, B. de Supinski, B.R. |
| Copyright Year | 1990 |
| Abstract | Heterogeneity continues to increase at all levels of computing, with the rise of accelerators such as GPUs, FPGAs, and other co-processors into everything from desktops to supercomputers. As a consequence, efficiently managing such disparate resources has become increasingly complex. CoreTSAR seeks to reduce this complexity by adaptively worksharing parallel-loop regions across compute resources without requiring any transformation of the code within the loop. Our results show performance improvements of up to three-fold over a current state-of-the-art heterogeneous task scheduler as well as linear performance scaling from a single GPU to four GPUs for many codes. In addition, CoreTSAR demonstrates a robust ability to adapt to both a variety of workloads and underlying system configurations. |
| Sponsorship | IEEE Computer Society |
| Starting Page | 2970 |
| Ending Page | 2983 |
| Page Count | 14 |
| File Size | 1545709 |
| File Format | |
| ISSN | 10459219 |
| Volume Number | 26 |
| Issue Number | 11 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-11-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Schedules Acceleration Graphics processing units Memory management Computational modeling Runtime Programming Heterogeneous, OpenMP, OpenACC, GPU, coscheduling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computational Theory and Mathematics Hardware and Architecture |
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