NDLI: A Reduced Switching Loss PWM Strategy to Eliminate Common-Mode Voltage in Multilevel Inverters

Content Provider	IEEE Xplore Digital Library
Author	Nho-Van Nguyen Tam-Khanh Tu Nguyen Hong-Hee Lee
Copyright Year	1986
Abstract	This paper introduces a novel pulse width modulation (PWM) technique to eliminate common-mode voltage in odd-multilevel inverters using the three zero common-mode vectors principles. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process can be fully explored in that active inverter as a switching time diagram and switching state sequence. Due to an unequal number of commutations of three phases in each sampling period, the switching loss is optimized by a proposed current-based mapping algorithm. The switching loss reduction can be up to 25% compared to the same PWM technique with nonoptimized algorithms. The PWM method has been then generalized as an equipotential PWM control, which is valid to both odd- and even-multilevel inverters . The theoretical analysis is verified by simulation and experimental results.
Sponsorship	IEEE Power Electronics Society
Starting Page	5425
Ending Page	5438
Page Count	14
File Size	4098600
File Format	PDF
ISSN	08858993
Volume Number	30
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vectors Inverters Pulse width modulation Switches Switching loss Equivalent circuits Pulse Width Modulation (PWM) Multilevel Inverter Common mode voltage switching loss Common-mode voltage (CMV) multilevel inverter pulse width modulation (PWM)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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