NDLI: Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support

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Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support

Content Provider	IEEE Xplore Digital Library
Author	Schafer, B.C.
Copyright Year	2009
Abstract	One of the biggest advantages of C-Based VLSI design over traditional RT-level design is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. So far previous works have focuses on either pruning the design space or by creating predictive models in combination with different metaheuristics. In this letter, we present a hierarchical method which makes use of modern HLS tool's options to synthesize functions as functional operators in order to explore these separately. Our method therefore explores each function separately and then performs a merging stage in order to obtain the overall dominating results. Moreover our proposed method detects if any changes in the behavioral description have happened between two exploration executions and only explores those functions which have been affected by the source code changes, while the results of the previous exploration are reused, thus enabling for incremental DSE. Results show that our method is very efficient.
Starting Page	51
Ending Page	54
Page Count	4
File Size	527621
File Format	PDF
ISSN	19430663
Volume Number	7
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Merging Space exploration Genetic algorithms Runtime Optimization Benchmark testing Predictive models incremental exploration Design space exploration (DSE) high-level synthesis
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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