NDLI: A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Content Provider	IEEE Xplore Digital Library
Author	Woong Choi Gyuseong Kang Jongsun Park
Copyright Year	1966
Abstract	This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2451
Ending Page	2462
Page Count	12
File Size	5192407
File Format	PDF
ISSN	00189200
Volume Number	50
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Viterbi algorithm Couplings Transistors Hardware IEEE 802.11n Standard Computer architecture Viterbi decoder Application-specific memory eDRAM embedded memory gain cell reference voltage generator
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

Power efficient low latency survivor memory architecture for Viterbi decoder

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A Low-Cost Multi-standard Audio Decoder Architecture Design

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

IEEE 802.11n: Performance evaluation of modified Viterbi metrics for TxBF, SDM and spatial spreading transceivers

Versatile refresh:low complexity refresh scheduling for high-throughput multi-banked eDRAM

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Similar Documents

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs

Power efficient low latency survivor memory architecture for Viterbi decoder

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A Low-Cost Multi-standard Audio Decoder Architecture Design

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

IEEE 802.11n: Performance evaluation of modified Viterbi metrics for TxBF, SDM and spatial spreading transceivers

Versatile refresh:low complexity refresh scheduling for high-throughput multi-banked eDRAM

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder