NDLI: Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire

Content Provider	IEEE Xplore Digital Library
Author	Haque, K. Beckett, P.
Copyright Year	1993
Abstract	Once largely the domain of space-borne applications, the effects of high energy charged particles on electronics systems are now also a concern for conventional terrestrial devices. The configuration memory within reconfigurable components, such as SRAM-based field-programmable gate arrays are particularly vulnerable to radiation-induced single event effects. We present a silicon on insulator (SOI)-based configuration memory system for use in a radiation hard reconfigurable system. A nonvolatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier, which results in a final structure that exhibits two unique characteristics enhancing its resistance to radiation. First, it is impossible for a radiation-induced event to permanently flip the configuration state. Second, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can very easily be detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. Failure estimates indicate a mean time between failures for a single cell to be in the order of 10³⁴ years.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	232
Ending Page	241
Page Count	10
File Size	1816247
File Format	PDF
ISSN	10638210
Volume Number	22
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	EPROM Field programmable gate arrays Logic gates CMOS integrated circuits Transistors Silicon-on-insulator Random access memory total ionization dose (TID) Auto-scrubbing field-programmable gate arrays (FPGAs) silicon on insulator (SOI) silicon on sapphire (SOS) single event upset (SEU)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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