NDLI: VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Content Provider	IEEE Xplore Digital Library
Author	Awais, M. Masera, G. Martina, M. Montorsi, G.
Copyright Year	1991
Abstract	This work presents the VLSI hardware implementation of a novel Belief Propagation (BP) algorithm introduced in [G. Montorsi, “Analog digital belief propagation,” IEEE Commun. Lett., vol. 16, no. 7, pp. 1106-1109, 2012] and named as Analog Digital Belief Propagation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by tracking their parameters. In particular, ADBP can deal with system variables that are discrete and/or wrapped. A variant of ADBP can then be applied for the iterative decoding of a particular class of non binary codes and yields decoders with complexity independent of alphabet size M, thus allowing to construct efficient decoders for digital transmission systems with unbounded spectral efficiency. In this work, we propose some simplifications to the updating rules for ADBP algorithm that are suitable for hardware implementation. In addition, we analyze the effect of finite precision on the decoding performance of the algorithm. A careful selection of quantization scheme for input, output and intermediate variables allows us to construct a complete ADBP decoding architecture that performs close to the double precision implementation and shows a promising complexity for large values of M. Finally, synthesis results of the main processing elements of ADBP are reported for 45 nm standard cell ASIC technology.
Sponsorship	IEEE Signal Processing Society
Starting Page	3965
Ending Page	3975
Page Count	11
File Size	2655847
File Format	PDF
ISSN	1053587X
Volume Number	62
Issue Number	15
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Complexity theory Signal processing algorithms Parity check codes Equations Wrapping Belief propagation VLSI decoder Analog Digital Belief Propagation APP estimation belief propagation decoder architecture iterative decoding non binary LDPC
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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