NDLI: Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs

Content Provider	IEEE Xplore Digital Library
Author	Ran Wang Chakrabarty, K. Eklow, B.
Copyright Year	1982
Abstract	2.5-D integration is emerging as the precursor to stacked 3-D ICs. Since the silicon interposer and micro-bumps in 2.5-D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 standard. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay defects in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. The proposed test technique is fully compatible with the IEEE 1149.1 architecture and can be controlled by the test-access port controller. We present HSPICE and ModelSim simulation results to demonstrate the effectiveness of fault detection. Simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach. We also present synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 standard. Synthesis results show that the cost of implementation of the architecture is negligible.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1410
Ending Page	1423
Page Count	14
File Size	3459404
File Format	PDF
ISSN	02780070
Volume Number	33
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Clocks Delays Integrated circuit interconnections Silicon Standards Computer architecture silicon interposer 25-D IC boundary scan interconnect test
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs

3D-IC interconnect test, diagnosis, and repair

Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs

Similar Documents

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs

3D-IC interconnect test, diagnosis, and repair

Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs