NDLI: Real-Time Stimulus Artifact Rejection Via Template Subtraction

Content Provider	IEEE Xplore Digital Library
Author	Limnuson, K. Hui Lu Chiel, H.J. Mohseni, P.
Copyright Year	2007
Abstract	This paper presents an infinite impulse response (IIR) temporal filtering technique for real-time stimulus artifact rejection (SAR) based on template subtraction. A system architecture for the IIR SAR algorithm is developed, and the operation of the algorithm with fixed-point computation is analyzed to obtain the number of bits for the internal nodes of the system, considering dynamic range and fraction length requirements for optimum performance. Further, memory initialization with the first recorded stimulus artifact is proposed and shown to significantly decrease the IIR system response time, especially when artifacts are highly reproducible in consecutive stimulation cycles. The proposed system architecture is hardware-implemented on a field-programmable gate array (FPGA) and tested using two sets of prerecorded neural data from a rat and an Aplysia californica (a marine sea slug) obtained from two different laboratories. The measured results from the FPGA verify that the system can indeed remove the stimulus artifacts from the contaminated neural data in real time and recover the neural action potentials that occur on the tail end of the artifact (as close as within 0.5 ms after the artifact spike). The root-mean-square (rms) value of the pre-processed stimulus artifact is reduced on average by a factor of 17 (Aplysia californica) and 5.3 (rat) post-processing.
Sponsorship	IEEE Circuits and Systems Society IEEE Engineering in Medicine and Biology Society
Page Count	10
File Size	1853267
Starting Page	391
Ending Page	400
File Format	PDF
ISSN	19324545
Volume Number	8
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Digital signal processing Blanking Real-time systems Timing Heuristic algorithms Signal processing algorithms template subtraction Closed-loop neuroprostheses field-programmable gate array (FPGA) neural recording neurostimulation stimulus artifact rejection
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Biomedical Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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