NDLI: Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip

Content Provider	IEEE Xplore Digital Library
Author	Krishna, T. Chen, C.-H.O. Woo-Cheol Kwon Li-Shiuan Peh
Copyright Year	1981
Abstract	As the number of on-chip cores increases, scalable on-chip topologies such as meshes inevitably add multiple hops to each network traversal. The best practice today is to design one-cycle routers, such that the low-load network latency between a source and destination is equal to the number of routers and links (that is, twice the hops) between them. Designers of operating systems, compilers, and cache coherence protocols often try to limit communication to within a few hops because on-chip latency is critical for their scalability. In this article, the authors propose an on-chip network called Smart (Single-cycle Multihop Asynchronous Repeated Traversal) that aims to present a single-cycle datapath all the way from the source to the destination. They do not add any additional fast physical express links in the datapath; instead, they drive the shared crossbars and links asynchronously up to multiple hops within a single cycle. They designed a router and link microarchitecture to achieve such a traversal, and a flow-control technique to arbitrate and set up multihop paths within a cycle. A place-and-route design at 45 nm achieves 11 hops within a 1-GHz cycle for paths without turns (9 hops for paths with turns). The authors observe 5 to 8 times reduction in low-load latencies across synthetic traffic patterns on an 8×8 chip multiprocessor, compared to a baseline one-cycle router network. Full-system simulations with Splash-2 and Parsec benchmarks demonstrate 27 and 52 percent reduction in runtime for private and shared level-2 designs, respectively.
Sponsorship	IEEE Computer Society
Starting Page	43
Ending Page	56
Page Count	14
File Size	1172335
File Format	PDF
ISSN	02721732
Volume Number	34
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Spread spectrum communication Digital communication Delays Repeaters Ports (Computers) System-on-chip virtualization high performance computing network on chip multicore processor repeated link networking
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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