NDLI: Bi-predictive motion estimation for HEVC on a graphics processing unit (GPU)

Content Provider	IEEE Xplore Digital Library
Author	Radicke, S. Hahn, J.-U. Wang, Q. Grecos, C.
Copyright Year	1975
Abstract	High Efficiency Video Coding (HEVC), the latest video compression standard, will play an important role in many multimedia applications in the foreseeable future. Its superior compression performance enables HEVC to be particularly suitable for high-definition videos in consumer electronics environments; however, it comes with the price of substantially high computational complexity. The HEVC encoding process, especially the Motion Estimation (ME), is very time consuming, which makes HEVC impractical for real-time applications at the moment. In this work, a hybrid encoding architecture with a set of algorithms is proposed, exploring a Graphics Processing Unit (GPU) to perform both uni-predictive and bi-predictive ME in a highly parallel manner. This reduces the complexity of the uni- and bipredictive ME on the Central Processing Unit (CPU) by up to 99% and 95% respectively, and brings significant overall time savings of up to 57.65% and 54.16% for the low delay P and the random access coding configurations respectively. The Rate-Distortion (RD) performance is only marginally affected in both cases.
Sponsorship	IEEE Consumer Electronics Society
Starting Page	728
Ending Page	736
Page Count	9
File Size	682975
File Format	PDF
ISSN	00983063
Volume Number	60
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics processing units Prediction algorithms Kernel Encoding Instruction sets Vectors Complexity theory Graphics Processing Unit (GPU) High Efficiency Video Coding (HEVC) Bi-Predictive Motion Estimation (ME)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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