NDLI: A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT

Content Provider	IEEE Xplore Digital Library
Author	Yusong Hu Ching Chuen Jong
Copyright Year	1991
Abstract	In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe-based scanning method based on the analysis of the dependency graph of the lifting scheme. With the new scanning method for multi-level 2D DWT, a high memory efficient scalable parallel pipelined architecture is developed. The proposed architecture requires no frame memory and a temporal memory of size only 3 N +682 for the 3-level DWT decomposition with an image of size N ×N pixels with 32 pixels processed concurrently. The elimination of frame memory and the small temporal memory lead to significant reduction in overall size. The proposed architecture has a regular structure and achieves 100% hardware utilization. The synthesis results in 90 nm CMOS process show that the proposed architecture achieves a better area-delay product by 60% and higher throughput by 97% when compared to the best existing design for the CDF (Cohen-Daubechies-Favreau) 9/7 2-D DWT.
Sponsorship	IEEE Signal Processing Society
Starting Page	4975
Ending Page	4987
Page Count	13
File Size	2562389
File Format	PDF
ISSN	1053587X
Volume Number	61
Issue Number	20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Memory management Throughput Hardware Finite impulse response filters Sequential analysis stripe-based scanning method Discrete wavelet transform (DWT) lifting- scheme scalable parallel multi-level 2-D DWT
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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