NDLI: Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer

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IEEE Transactions on Nanotechnology publication information

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A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI Interconnection

A Size-Dependent Continuum Model for Nanoscale Circular Plates

Synthesis of Zinc Oxide Nanostructures by Microheaters in the Ambient Environment

Nanorobot Controlled by Optical Tweezer Spin for Microsurgical Use

Non-Surface-Treated Au/ZnO Schottky Diodes Using Pre-Annealed Hydrothermal or Sol-Gel Seed Layer

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Automatic Morphological Measurement of the Quantum Dots Based on Marker-Controlled Watershed Algorithm

Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer

Design of a Hybrid Memory Cell Using Memristance and Ambipolarity

Reliability of Sensors Based on Nanowire Networks With Either an Equilateral Triangle Lattice or a Hexagonal Lattice Structure

Stochastic Quantum Inductive Circuit With Discrete Charge

Carbon Nanofiber Nanoelectrode Array: Effect of Process Conditions on Reliability

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Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer

Content Provider	IEEE Xplore Digital Library
Author	Wei Wei Jie Han Lombardi, F.
Copyright Year	2002
Abstract	This paper presents the characterization and design of a static random access memory (SRAM) cell at nanoscale ranges. The proposed SRAM cell incorporates a single-electron (SE) turnstile and an SE transistor/MOS circuit in its operation, hence the hybrid nature. Differently from previous cells, the hybrid circuit is utilized to sense (measure) on a voltage basis the presence of at least an electron as stored in memory, while the turnstile enables the SE transfer in and out of the storage node. The two memory operations (read and write) are facilitated by utilizing these hybrid circuits; moreover, the proposed SRAM cell shows compatibility with MOSFET technology. HSPICE simulation shows that the proposed SRAM cell operates correctly at 45 and 32 nm with good performance in terms of propagation delay, signal integrity, area, stability, and power consumption. The extension of the aforementioned hybrid design to a ternary content addressable memory cell is also presented.
Sponsorship	IEEE Nanotechnology Council
Starting Page	57
Ending Page	70
Page Count	14
File Size	1139652
File Format	PDF
ISSN	1536125X
Volume Number	12
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit modeling Tin Logic gates Random access memory Delay MOSFETs ternary content addressable memory (TCAM) Memory cell design single-electron transistor (SET) static random access memory (SRAM)
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Z-TCAM: An SRAM-based Architecture for TCAM

Nano-Reconfigurable Cells With Hybrid Circuits of Single-Electron Transistors and MOSFETs

Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells

Design and Analysis of Power-Efficient Quasi-Adiabatic Ternary Content Addressable Memory (QATCAM)

A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines

Ternary static random access memory using quantum dot gate field-effect transistor

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer

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