NDLI: CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits

Content Provider	IEEE Xplore Digital Library
Author	Yonggang Chen Jaeger, R.C. Suhling, J.C.
Copyright Year	2001
Abstract	This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm² using only a 1.5 μm process. The arrays are sequentially scanned by an on-chip counter, producing efficient stress measurement, and the sensors resolve normal and shear stresses on the surface of the die with resolution below 1 MPa. The CMOS sensor chips have been used to map stress over a large portion of the die in chip-on-beam and encapsulated chip-on-beam samples, as well as a ceramic dual-in-line package with its cavity filled with underfill material. Finite-element simulation results correlate well with the measured stress distributions. The experimental results from these chips are used to validate finite-element simulation models, and the array designs can be used as subarrays in much larger test chips.
Sponsorship	IEEE Sensors Council
Starting Page	2066
Ending Page	2076
Page Count	11
File Size	2481756
File Format	PDF
ISSN	1530437X
Volume Number	13
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Transistors Sensor arrays CMOS integrated circuits Semiconductor device measurement Mirrors Silicon stress Complementary-metal-oxide semiconductor (CMOS) current mirror sensors piezoresistance PiFET sensor array sensors
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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