NDLI: Relationship Between Wafer-Level Warpage and Cu Overburden Thickness Controlled by Isotropic Wet Etching for Through Si Vias

Content Provider	IEEE Xplore Digital Library
Author	Jae Woong Choi Lee Guan Ong Hong Yu Li Soon Wook Kim Hwang, G.H. Jang, S.L.H. Murthy, R. Kiat, E.T.S.
Copyright Year	2011
Abstract	In this paper, we developed an isotropic wet etching process in a capsule-type bevel etch chamber to reduce a Cu overburden of through Si via (TSV) for less wafer-level warpage with 300 mm wafers. We report the relationship between the wafer-level warpage and the Cu overburden thicknesses controlled by the isotropic wet etching with diluted solution of hydrogen peroxide and sulfuric acid, which is widely used for Cu wet etching. After Cu filling by electroplating, there are humps at the top of the TSVs; therefore, the isotropic wet etching can be considered as a solution to etch away the Cu overburden without any damages on the TSVs. We modified the capsule-type bevel etch chamber to avoid serious attack on TSVs at the center area of the wafer caused by the etchant delivery path. We also adjusted the process parameters to have a controllable Cu etch rate. The etch rate of ~ 0.2 μm/s and the uniformity of ~ 3% were achieved. The overburden was able to be etched up to 3 μm m from the initial Cu overburden. While the Cu overburden decreased during the isotropic wet etching, the TSVs were protected from the etchant because of the humps at the top of the TSVs. After the Cu electroplating, there was a grain size difference between the Cu at TSV and the Cu at field area. Because the microstructural difference caused a galvanic corrosion during the wet etching, the etch rate of the adjacent Cu around TSV was faster than the Cu at any other area. That resulted in exposure of dielectric layer at the adjacent area around TSVs when the Cu overburden was etched heavily. It may be another protection mechanism of TSV during the isotropic wet etching. The wafer-level warpage of the wafer with the Cu overburden etched up to 3 μm after the annealing decreased by 50% from that of the wafer with the initial Cu overburden. The wafer-level warpage exhibited a linear relationship with the Cu overburden thickness controlled by the isotropic wet etching.
Starting Page	1820
Ending Page	1825
Page Count	6
File Size	1476721
File Format	PDF
ISSN	21563950
Volume Number	3
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wet etching Through-silicon vias Annealing Silicon Chemicals Process control wafer-level packaging Cu filling Cu overburden galvanic corrosion isotropic wet etch microstructure of Cu through Si via (TSV) wafer warpage
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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