NDLI: High-speed rate estimation based on parallel processing for H.264/AVC CABAC encoder

Content Provider	IEEE Xplore Digital Library
Author	Wei Li Fuzheng Yang Guangliang Ren
Copyright Year	1975
Abstract	The advanced video codec of H.264/AVC has been extensively employed for data compression for efficient video storage or transmissions. However, its intensive computational complexity causes a bottleneck for its real-time applications. Simultaneously, the sequential operation in the normal encoding process is not favorable with regard to hardware implementations. In this paper, a high-speed and accurate bit-rate estimation scheme is proposed to skip the actual entropy engine of context-adaptive binary arithmetic coding (CABAC), which is useful for reducing the computational complexity and saving the encoding time in H.264/AVC rate distortion (RD) optimization for mode decision. The characteristics of syntax elements and the principle of CABAC are firstly analyzed. Then guided by the spirit of parallel processing, a novel algorithm is constructed to estimate the bit-rate in RD mode decision. The proposed method significantly accelerates the encoding process while well maintaining the video quality, and is well suited to hardware implementations due to its feature of parallel processing¹.
Sponsorship	IEEE Consumer Electronics Society
Starting Page	237
Ending Page	243
Page Count	7
File Size	1846348
File Format	PDF
ISSN	00983063
Volume Number	59
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Estimation Context Video coding Indexes Parallel processing Syntactics parallel processing CABAC rate estimation mode decision
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

Fast Rate Estimation for H.264/AVC CAVLC Encoder Based on Parallel Processing

A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video

Improved CABAC design in H.264/AVC for lossless depth map coding

Complexity-Efficient Rate Estimation for Mode Decision of the HEVC Encoder

One-round renormalization based 2-bin/cycle H.264/AVC CABAC encoder

A low-cost and high efficiency entropy encoder architecture for H.264/AVC

A scheme of parallel arithmetic coding

A high speed real time multi-bin CABAC encoder for ultra high resolution video

High-speed rate estimation based on parallel processing for H.264/AVC CABAC encoder

Similar Documents

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

Fast Rate Estimation for H.264/AVC CAVLC Encoder Based on Parallel Processing

A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video

Improved CABAC design in H.264/AVC for lossless depth map coding

Complexity-Efficient Rate Estimation for Mode Decision of the HEVC Encoder

One-round renormalization based 2-bin/cycle H.264/AVC CABAC encoder

A low-cost and high efficiency entropy encoder architecture for H.264/AVC

A scheme of parallel arithmetic coding

A high speed real time multi-bin CABAC encoder for ultra high resolution video

High-speed rate estimation based on parallel processing for H.264/AVC CABAC encoder