NDLI: SPAD Image Sensor With Analog Counting Pixel for Time-Resolved Fluorescence Detection

Content Provider	IEEE Xplore Digital Library
Author	Pancheri, L. Massari, N. Stoppa, D.
Copyright Year	1963
Abstract	This paper presents a 32 × 32 pixel image sensor for time-gated fluorescence lifetime detection based on single-photon avalanche diodes. The sensor, fabricated in a high-voltage 0.35- μm CMOS technology, uses an analog counting approach to minimize the area occupation of pixel electronics while maintaining a nanosecond timing resolution and shot-noise-limited operation. The all nMOS pixel is formed by 12 transistors and features 25- μm pitch and 20.8% fill factor. The chip includes a phase-locked loop circuit for gating window generation, working at a maximum repetition frequency of 40 MHz, while the sensor can be gated at frequency up to 80 MHz using an external delay generator. Optical characterization with a picosecond-pulsed laser showed a minimum gating window width of 1.1 ns. Example images acquired in both continuous and time-gated mode are presented, together with a lifetime image obtained with the sensor mounted on a fluorescence microscope.
Sponsorship	IEEE Electron Devices Society
Starting Page	3442
Ending Page	3449
Page Count	8
File Size	2165750
File Format	PDF
ISSN	00189383
Volume Number	60
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Photonics Logic gates Timing Radiation detectors Image resolution Phase locked loops time gating Analog counter CMOS image sensor fluorescence lifetime imaging (FLIM) single-photon avalanche diode (SPAD)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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