NDLI: A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Ho Chen Tsin-Yuan Chang
Copyright Year	1993
Abstract	In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the distributed arithmetic (DA)-precision bit length, a hardware sharing architecture that reduces the hardware cost, and the proposed time scheduling strategy arranges different dimensional computations in that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach a hardware utilization of 100%. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits based on test image simulations. In addition, the proposed hardware sharing architecture employs a binary signed-digit DA architecture that enables the arithmetic resources to be shared during the four time slots. For this reason, the proposed 2-D DCT core achieves high accuracy with a small area and a high throughput rate and is verified using a TSMC 0.18-μm 1P6M CMOS process chip implementation. Measurement results show that the core has a latency of 84 clock cycles with a 52 dB peak-signal-to-noise-ratio and is operated at 167 MHz with 15.8 K gate counts.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	655
Ending Page	664
Page Count	10
File Size	1970241
File Format	PDF
ISSN	10638210
Volume Number	20
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Hardware Computer architecture Registers Adders Accuracy space-time scheduling (STS) Binary signed-digit (BSD) discrete cosine transform (DCT) distributed arithmetic (DA)-based
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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