NDLI: A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

Content Provider	IEEE Xplore Digital Library
Author	Ubal, R. Sahuquillo, J. Petit, S. Lopez, P. Kaeli, D.
Copyright Year	1990
Abstract	Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Expanding the width of the instruction window can be highly beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory latencies. Based on the Validation Buffer (VB) architecture (a previously proposed out-of-order retirement, checkpoint-free architecture for single processors), this paper proposes a cost-effective, scalable, out-of-order retirement multiprocessor, capable of enforcing sequential consistency without impacting the design of the memory hierarchy or interconnect. Our simulation results indicate that utilizing a VB can speed up both relaxed and sequentially consistent in-order retirement in future multiprocessor systems by between 3 and 20 percent, depending on the ROB size.
Sponsorship	IEEE Computer Society
Starting Page	1361
Ending Page	1368
Page Count	8
File Size	1217413
File Format	PDF
ISSN	10459219
Volume Number	23
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Retirement Out of order Multicore processing Pipelines sequential consistency. Out-of-order retirement multicore processors validation buffer
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computational Theory and Mathematics Hardware and Architecture

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