NDLI: Silicon-Based Dynamic Synapse With Depressing Response

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IEEE Computational Intelligence Society Information

Silicon-Based Dynamic Synapse With Depressing Response

Content Provider	IEEE Xplore Digital Library
Author	Dowrick, T. Hall, S. McDaid, L.J.
Copyright Year	2012
Abstract	A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is “weighted” by a voltage applied to the second terminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltage determines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal-oxide-semiconductor field-effect transistor operating in subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal-oxide-semiconductor process, alongside theoretical and simulation results, confirm the ability of the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.
Page Count	13
File Size	1009125
Starting Page	1513
Ending Page	1525
File Format	PDF
ISSN	2162237X
Volume Number	23
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Neurons Discrete cosine transforms Hardware Mathematical model MOSFETs spike-timing-dependent plasticity (STDP) Depressing synapses neural network hardware neuromorphic engineering
Content Type	Text
Resource Type	Article
Subject	Artificial Intelligence Computer Networks and Communications Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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