NDLI: Demonstration of Split-Gate Type Trigate Flash Memory With Highly Suppressed Over-Erase

Content Provider	IEEE Xplore Digital Library
Author	Kamei, T. Yongxun Liu Matsukawa, T. Endo, K. O'uchi, S. Tsukada, J. Yamauchi, H. Ishikawa, Y. Hayashida, T. Sakamoto, K. Ogura, A. Masahara, M.
Copyright Year	1980
Abstract	The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V_t) variations before and after NOR-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L_CG) of 176 nm show much smaller Vt distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV_DS) is higher than 3.1 V even the L_CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled NOR-type flash memory with highly suppressed over-erase.
Sponsorship	IEEE Electron Devices Society
Starting Page	345
Ending Page	347
Page Count	3
File Size	486338
File Format	PDF
ISSN	07413106
Volume Number	33
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Split gate flash memory cells Ash Logic gates Transistors Wet etching Channel hot electron injection Fabrication trigate Flash memory over-erase split gate
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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