NDLI: Sub-50-nm <formula formulatype=inline><tex Notation=TeX>$hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ </tex></formula> MOSFETs With Various Barrier Layer Materials

Content Provider	IEEE Xplore Digital Library
Author	Fei Xue Aiting Jiang Han Zhao Yen-Ting Chen Yanzhan Wang Fei Zhou Lee, J.
Copyright Year	1980
Abstract	Sub-50-nm In_0.7Ga_0.3As MOSFETs with high-k dielectric Al₂O₃ have been demonstrated and investigated. The device performance of buried-channel In_0.7Ga_0.3As MOSFETs with various barrier layer materials (i.e., InP and InAlAs) has been analyzed and compared to that of devices without a barrier layer. The 40-nm-gate-length In_0.7Ga_0.3 As MOSFETs with InP/InAlAs barrier exhibit a subthreshold swing of 130 mV/dec, a drain-induced barrier lowering of 174 mV/V, and an extrinsic transconductance of 570 mS/mm at V_ds = 1 V. Scaling behaviors of buried-channel In_0.7Ga_0.3As MOSFETs with and without a barrier layer material have also been analyzed.
Sponsorship	IEEE Electron Devices Society
Starting Page	32
Ending Page	34
Page Count	3
File Size	430526
File Format	PDF
ISSN	07413106
Volume Number	33
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Indium phosphide Logic gates Indium gallium arsenide Transconductance Aluminum oxide metal–oxide–semiconductor field-effect transistor (MOSFET) Atomic layer deposition high-$k$ high mobility InGaAs
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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