NDLI: Quadrant-Based Online Spatial and Temporal Compressive Acquisition for CMOS Image Sensor

Content Provider	IEEE Xplore Digital Library
Author	Milin Zhang Bermak, A.
Copyright Year	1993
Abstract	The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1525
Ending Page	1534
Page Count	10
File Size	2062659
File Format	PDF
ISSN	10638210
Volume Number	19
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image coding CMOS image sensors Image storage Image sensors Logic arrays Sensor arrays Logic circuits Hardware Virtual prototyping PSNR online quadrant-based temporal compression algorithm Compressive acquisition digital pixel sensor
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm

Block-Based CS in a CMOS Image Sensor

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

Adaptive Multiple-Resolution CMOS Active Pixel Sensor

CMOS Camera With In-Pixel Temporal Change Detection and ADC

A scalable and programmable simplicial CNN digital pixel processor architecture

Quadrant-Based Online Spatial and Temporal Compressive Acquisition for CMOS Image Sensor

Similar Documents

Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm

Block-Based CS in a CMOS Image Sensor

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

Adaptive Multiple-Resolution CMOS Active Pixel Sensor

CMOS Camera With In-Pixel Temporal Change Detection and ADC

A scalable and programmable simplicial CNN digital pixel processor architecture

Quadrant-Based Online Spatial and Temporal Compressive Acquisition for CMOS Image Sensor