NDLI: Prediction and Comparison of High-Performance On-Chip Global Interconnection

Content Provider	IEEE Xplore Digital Library
Author	Yulei Zhang Xiang Hu Deutsch, A. Engin, A.E. Buckwalter, J.F. Chung-Kuan Cheng
Copyright Year	1993
Abstract	As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global interconnect based on on-chip transmission line (T-line) technology. We perform a group of experiments using six different global interconnection structures to discover their differences in terms of latency, energy per bit, throughput, area, and signal integrity over several technology nodes. Our results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication. Our results also show that on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1154
Ending Page	1166
Page Count	13
File Size	1783633
File Format	PDF
ISSN	10638210
Volume Number	19
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire Delay Power system interconnection Repeaters Throughput Power transmission lines System-on-a-chip Intersymbol interference Degradation Performance analysis transmission line On-chip global interconnect passive equalization performance prediction
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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