NDLI: CMOS UWB Multiplier

Content Provider	IEEE Xplore Digital Library
Author	Mincica, M. Pepe, D. Zito, D.
Copyright Year	2004
Abstract	A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 × 700 μm². The overall power consumption is 3.7 mW from a 1.2-V power supply. In the case of input monocycle pulses with duration time of 700 ps, the measurements show an input-output energy ratio equal to 2, a conversion gain of 12.7 dB at intermediate frequencies in the range of 0.001-10 MHz for input tones in the range of 2-4 GHz, a noise figure of 14.4 dB (minimum) and compression points of -3.5 and -2 dBm for the two inputs. The performance of the proposed multiplier favorably compares with the state of the art.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	570
Ending Page	574
Page Count	5
File Size	414859
File Format	PDF
ISSN	15497747
Volume Number	58
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency CMOS integrated circuits MOSFET circuits Wideband Linearity Mixers Noise measurement ultrawideband (UWB) CMOS multiplier radar radio-frequency (RF) integrated circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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