NDLI: Multiclass Flow Line Models of Semiconductor Manufacturing Equipment for Fab-Level Simulation

Content Provider	IEEE Xplore Digital Library
Author	Morrison, J.R.
Copyright Year	2004
Abstract	For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the customer delay is well structured and we develop a recursion to calculate it. The recursions provide an alternative to the elementary evolution equations. By considering batch arrivals and restricting the structure of the model, the recursions can require nearly one order of magnitude less computation than is otherwise possible. Flow lines can be used as models for semiconductor manufacturing equipment such as multicluster or clustered photolithography tools. The models allow for internal wafer buffers and setups that are wafer location dependent. The models have shown to be very accurate in tests with data from clustered photolithography tools in production. As such, the models may serve as good candidates to improve the fidelity of existing equipment models in fab level simulation.
Sponsorship	IEEE Robotics and Automation Society
Starting Page	81
Ending Page	94
Page Count	14
File Size	581000
File Format	PDF
ISSN	15455955
Volume Number	8
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Virtual manufacturing Semiconductor device manufacture Semiconductor device modeling Computational modeling Lithography Throughput Delay Production Robots Equations semiconductor manufacturing automation Fab-level simulation flow line photolithography cluster tools
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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