NDLI: Reconfigurable Low Area Complexity Filter Bank Architecture Based on Frequency Response Masking for Nonuniform Channelization in Software Radio Receivers

Content Provider	IEEE Xplore Digital Library
Author	Mahesh, R. Vinod, A.P.
Copyright Year	1965
Abstract	The most computationally demanding block in the digital front-end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Channelizers are employed in the SDR receivers for extracting individual channels (frequency bands) from the digitized wideband input signal. Reconfigurability and low complexity are the two key requirements in an SDR channelizer. A new reconfigurable filter bank (FB) architecture based on frequency response masking (FRM) for SDR channelizers is proposed. The proposed FB offers reconfigurability at the architectural level and at the channel filter level and is capable of extracting channels of nonuniform bandwidths corresponding to multiple wireless communication standards from the digitized wideband input signal. Design examples show that the proposed FB offers multiplier complexity reduction of 84% over the conventional per-channel (PC) approach, which is best suitable for the extraction of channels of nonuniform bandwidth. The proposed FB has been synthesized on 0.18 μm complementary metal oxide semiconductor (CMOS) technology and compared with the PC approach. Synthesis results show that the proposed FB offers area reduction of 85%, power reduction of 48.5%, and improvement in speed of 56.7% over the PC approach. The proposed FB has been implemented on Xilinx Virtex 2v3000ff1152-4 FPGA and tested using real-time inputs from a vector signal generator.
Starting Page	1241
Ending Page	1255
Page Count	15
File Size	1612234
File Format	PDF
ISSN	00189251
Volume Number	47
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Filter banks Complexity theory Bandwidth Receivers Delay
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Aerospace Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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